Electronic resolver



July 22, 1969 G. R. GRADO ELECTRONIC RESOLVER 3 Sheets-Sheet 1 FiledMarch 25. 1966 ji/vewrae. 6/4952 TR. Gznoa 4/1125 ,6

July 22, 1969. G. R. GRADO ELECTRONIC RESOLVER 3 Sheets-Sheet 2 FiledMarch 25, 1966 a T 6 WW m W w V P W! Th w M a 0 M a w M M 5 m. n a 0 m mm w m w my w m M w a m A 4 D m o m m w. 2 M w (v ID D o O O O O D e 8.A5 .HF. H C l MEL" FCHA o M M 0 0 m A .A C .c 5 s F M 3 w 0 w a w m A wm m L L w VEC TOR I00 SIN 9 ROTATION 0F AXES T a NM 5 N we r G 0 m w 0RIP T 5 w a 4 M E a m a 5 0 N? v! 5 m :0 Fl

United States Patent Office Patented July 22, 1 969 U.S. Cl. 235-189 18Claims ABSTRACT OF THE DISCLOSURE The disclosure concerns an electronicresolver capable of polar to rectangular conversion, rectangular topolar conversion and rotation of axes conversion; and also capable ofadditional modes of operation including rate mode.

The present invention relates generally to computing equipment, and morespecifically concerns electronic resolvers for use in such equipment.

Resolvers are useful in computing systems to provide one or more outputsthat depend upon one or more inputs, For example, the simulation ofthree dimensional, six degree of freedom systems usually requires theuse of accurate coordinate transformation so that rectangularto-polarand polar-to-rectangular conversions may be effected with a high degreeof precision and reliability.

It is a major object of the invention to provide an unusually etfectiveand reliable resolver characterized by combinations and sub-combinationsof the following features and advantages: the resolver accepts inputrepresentative of an angle and of a scalar quantity R and produces sin 9and cosine 0 sinusoid generation output, and R sin 0, R cos 0 output forpolar to rectangular conversion; the resolver also accepts R input toproduce R sin 0 and R cos 0 output for polar to rectangular conversion;the resolver accepts X and Y input as well as 6 input to produce Y cos 0X sin 0 output and X cos 6+Y sin 19 output for rotation of axes mode;the resolver accepts X and Y inputs and provides outputs /X +Y and tanY/X for rectangular to polar transformation; and the resolver acceptsrate input such as d 6 and generates continuous sine and cosinefunctions for rate mode operation. As to the latter, switching circuitrypermits the sine function to appear as a continuous wave even though theinput angle 0 passes through a reverse cycle. Also the rate logicaccepts an extremely wide range of rate inputs. Finally, the equipmentfor sine and cosine function generation is simplified by the provisionfor inversion of 6 input to provide both 0 and 0 input to the functiongenerators.

Basically, the resolver comprises sine and cosine generators havingsumming paths for fixed amplitude signals associated with a 21r radianor 360 degree range and for an input signal 0 variable within limitsassociated with the boundaries of that range; switch means connected incircuit with such paths to control signal application to the generatorsvia said paths; and control logic to operate the switches in suchrelation to change of 0 between such limits that the generators willgenerate sine and cosine values of 0. Typically, the sine generator hasassociated summing paths for input signals defined as 0, 20, 11' and 1r;the cosine generator has associated summing paths for input signalsdefined as 0, -26 and 1r/ 2; the switch means is connected in circuitwith certain of such paths to control application of the signals 20, 1rand -1r to the generators; and the control logic operates the switchesin such relation to values of 0 between upper and lower limitsassociated with 11' and 1r that the generators generate sine and cosineversions of 0.

As will appear, the resolver may include multiplier means connectible toreceive input via the generators, and paths connected to supply scalarinput to the multipliers so that the latter produce output products ofthe generator and scalar inputs. For example, such output products mayinclude values -R sin 0 and R cos 0, and also R cos 0 and R sin 0. Asregards rotation mode, the multiplier means may include primarymultipliers to receive X scalar input and secondary multipliers toreceive Y scalar input, the multiplier outputs connected to yieldoutputs Y cos 9 X sin 6 and X cos 0 Y sin 0. For rate mode, the resolvermay typically include means to supply an integrated version of an inputd0/dt to the 0 paths to the generators. Such means may typically includean integrator having output connected in series with such 0 paths,inputs for positive and negative versions of da/dr, and means to varythe application of at least one of the inputs to the integrator at timeswhen 9 passes through its limits, thereby to produce a continuous wave.Finally, the invention contemplates the provision for conversion ofrectangular to polar coordinates in an unusual and advantageous mannerwhich will hereafter appear.

These and other objects ad advantges of the invention, as well as thedetails of an illustrative embodiment, will be more fully understoodfrom the following detailed description of the drawings, in which:

FIG. 1 is a block diagram of one preferred form of the resolver;

FIG. 2 is a block diagram of control logic for the FIG. 1 resolver;

FIG. 3 illustrates sine and cosine output waveforms as related to inputangle and also to resolver switch states;

FIG. 4 illustrates one form of sine or cosine generator usable in theresolver;

FIG. 5 illustrates development of a sine curve by the FIG. 4 generator;and

FIG. 6 illustrates graphically a transformation of axes.

As mentioned, the resolver incorporates sine and cosine generators andsumming paths for fixed amplitude input signals associated with apreselected radian range, and for an input signal (arbitrarilydesignated as 0) which is variable within limits associated with theboundaries of the selected radian range. As one example of this, FIG. 1illustrates sine and cosine generators 10 and 11, and groups 12 and 13of summing paths for sine and cosine generator input signals. Group 12typically includes path 14 for a positive reference input signal fromsource 15 and of fixed amplitude associated with a -{-r radian upperlimit; path 16 for a negative reference input signal from source 17 andof fixed amplitude associated with a 1r radian lower limit; path 18 foran input signal representative of an input angle 0 variable betweenlimits delineating an associated 211' radian range; and path 19 for aninput signal representative of the input value 20. As to the latter, the0 input at 50 is typically passed to an inverter 51 to produce 0 at 52and at take off point 520. Such paths have summing connection at inputpoint 20 to the sine generator 10.

In like manner, the group 13 includes path 21 for an input signalrepresentative of the input value 20; path 22 for an input signalrepresentative of the input value 0; and path 23 for a positivereference input signal from source 24, and of fixed amplitude associatedwith a 1r/ 2 radian value. These paths also have summing connection atinput point 30 to cosine generator 11. Appropriate resistors may be usedin the paths, as illustrated, for proper relative signal leveldevelopment.

Also, as was previously mentioned the resolver includes switch meansconnected in circuit with certain of the summing paths to control signalapplication to the generators via the paths. In the illustrated example,switches 25, 26 and 27 are connected in series circuit with respectivepaths 14, 16 and 19 to control application of the signals 1r, -1r and 26to the sine generator, and switch 28 is connected in path 21 to controlapplication of the signal -26 to the cosine generator.

Control logic is provided in accordance with the invention to operatethe switches in such relation to change of 6 between the limitsassoicated with the boundaries of the preselected radian range that thegenerators will generate sine and cosine versions of 6. In theparticular example, the control logic places the switches in on and offstates in accordance with the associated waveforms 25a, 26a, 27a and 28aseen in FIG. 3. Accordingly, as the 6 input to paths 18 and 22 variesover the 21r range between 11- and +1r as seen in ramp or sawtoothwaveform 40 in FIG. 3, the generators 10 and 11 produce sin 6 and cos 6outputs designated by waveforms 41 and 42, and appearing at outputpoints 43 and 44 in FIG. 1. Note also sin 6 output point 43a, at theoutput of amplifier 53 and sin 6 output at the output of inverter 431;.Similarly, see cos 6 at 44, at output of amplifier 5'4, and cos 6 at 44aat output of inverter 441). In this regard, such 6 input may haveamplitude represented in terms of volts, so that at 6:0 volts in FIG. 3,the sine and cosine output voltages are and 100 respectively.

In a typical example, digital-to-analog switches 25 and 26, indicated asDA2 and DA3, have i100 volts reference (equivalent to i180 degreesrelative to 6 input) applied to their respective inputs. Their outputsare also connected to the input of the sine generator. The 6 output fromthe inverter :51 is applied to switches 27 and 28, indicated as DA4 andDA5. A l00-volt input at 23 to the cosine generator applies the correctreference value for cosine generation [sin (90+6)=cos 61.

The high-gain amplifiers at 53 and 54 in FIG. 1 respectively have thesine and cosine generators 10 and 11 connected as feedbacks, making eacha variable gain amplifier. Assuming a 6 input of zero volts (each sineand cosine generator is typically scaled to an output of 1.8 degrees pervolt input), the output of the sine generator is Zero volts, and thecosine generator output is +100 volts. These values correspond to thecorrect sine and cosine values of sin 6 at 6:0 and cos 6=sin (90+6).

The upper part of FIG. 3 shows a 6 input at zero degrees of zero volts,and a sine and cosine output voltage of 0 and 100, respectively. Thelower part of the figure shows the condition of the switches; zero voltsis the off or no output condition, and 6 volts isthe on condition. Allthe switches are oil in the first forward quadrant (0 to +90 degrees).Maximum excursions of 6, sine, and cosine are all i100 volts. Note thatas the second forward quadrant is entered, switches DA2 and DA4 areturned on as a comparator in the resolver logic of FIG. 2 senses thecosine value 42 crossing the zero axis. DA2 and DA4 stay turned onwhenever the 6 input is between +90 and +180 degrees (+50 and +100volts). Returning again to an assumed 6 input of zero (all switchesoff), if 6 goes negative, DA is turned on; as 6 is increased negativelypast 90 degrees, DA3 and DA4 are turned on, and DA5 remains on.

The outputs to the sine generator are 6, 26 at DA4 and and 180 degreesat DA2 and DA3, respectively. The inputs to the cosine generator 11 are-26 at DA5, 6, and -90 through a suitable resistor 56. The 6 input istypically scaled to 1.8 degrees per volt, so that the 26 input would be3.6 degrees per volt, establishing a ratio between these two inputs of2: 1. Assuming 620 degrees, and rising to not more than +90 degrees (allswitches oil), and the input variables to the sine and cosine generatorsare +6. As the input passes +90, the comparator 57 with C and E outputssenses the output cosine value going from positive to negative (FIG. 3),i.e. C goes false (0 volts) and 6 goes true. The output of the NAND-Gate 64 with inputs A, C and D Ai then goes false, causing the outputsof the two NAND-Gates 59 and 60 that control switches DA2 and DA4,respectively, to go true, thereby turning the switches on. Switch DA4applies 180 degrees (+26) to the sine generator input. At the same time,switch DA2 applies +180 degrees to the sine generator input; thesevalues cancel each other, and the sine generator input is still the 6input, or degrees. However, as 6 continues to increase, an algebraicsummation (626=6) is being performed, the resultant of which drives thesine generator input junction 20 toward 0 volt (+180 degrees). In a likemanner, it can be seen how switch DA5 affects the cosine generator inputwhen a negative 6 is applied, and how DA3 and DA4 affect the sinegenerator when a 6 input of -90 degrees (-50 volts) is reached.

The logic which controls these switches may be considered to includecomparator -61 to sense the polarity of the 6 input (+6=A true) and thecomparator 57 to sense the polarity of the cosine generator output (+cos6=C true). Inverters 62 and 63 are provided to generate K and 6 when Aand C are false. For initial conditions, assume 650. With 6 goingpositive and the cosine output positive, A and C out of the comparatorare true. When 6+5O volts, the output of the cosine generator crossesthrough zero, going negative. The C comparator senses the axis crossing;C goes false (0 volt) and 5 goes true (6 volts).

A series of NAND-Gates is shown at 58, 64, 111, 112, 200 and 201. Theassumed initial conditions of 650 volts (0 degrees) but not more than+50 volts (+90 degrees) makes A, C, and m true, which does not satisfyany of the NAND-Gate input requirements, and the outputs of DA2, DA3,DA4 (which are gated) and DA5 (not gated) are all at 0 volts; i.e. allthe DA switches are turned off. As the voltage at 6 exceeds +50, C goesfalse, and the NAND-Gate 64 with terms A, 6, and 1T1 at its input goesfalse, causing the output of the gates 59 and 60 controlling DA2 and DA4to go true, thereby turning those switches on. Similarly, if the 6 inputgoes negative from zero, K goes true, and DA5 is turned on. As 6 exceeds50 volts (90 degrees) true K, 0, and nsr at gate 58 cause DA3 and DA4 toturn on. This completes the description of the FIG. 2 sine and cosinemode switching logic, through i180 degrees.

The invention also contemplates the provision of multiplier means 73 and74 connectible, as by relays Kl, to receive input from the sine andcosine generators via paths 210213, as well as paths 214-217 connectedto supply selected scalar inputs, indicated as R and R, to themultipliers, whereby the latter are operable to produce output productsof the inputs. In this regard, if relays K-1 are disabled, input paths210-213 are available for independent use, as via the input points 77,77a, 78 and 78a. The multiplier outputs are available at 79 and 80.Thus, in the event of energization of relays K4, the primary multipliers73 and 74 receiving R and R input on paths 214217, and sine 6 and cos 6input on paths 210-213 produce as outputs the values R sin 6 and R cos6, usuable for example in polar to rectangular conversion.

The invention also contemplates that the multiplier means may includesecondary amplifiers 85 and 86 connected to receive selected scalarinputs, as for example are indicated at R and to produce as outputs thevalues R cos 6 and R sin 6, usuable for example in dual polar torectangular conversion, i.e. for converting two polar vectors torectangular coordinates. This mode is enabled when relays K-2 areenergized, for connecting the secondary multipliers with the i sin 6 andt cos 6 inputs. In the event of de-energization of relays K2, inputpoints 88, 88a, 89 and 89a are available for input to the multipliers 85and 86. The secondary multiplier outputs appear at and 161.

The resolver is also able to perform a rotation or transformation ofaxes computation, defined by the following two equations and exemplifiedin FIG. 6:

Y =Y cos 6X sin 6 (1) X =X cos 0+Y sin 6 (2) where, the terms X and Ydefine the coordinates of a point in the first rectangular coordinatesystem, and the terms X and Y define the coordinates of the same pointin a second rectangular coordinate system which is rotated through anangle 0 about the origin of the first coordinate system. Thus, thevalues Y and X represent outputs of the resolver in the rotation of axesmode. As one example of this, the relays K-l, K-2 and K-3 in FIG. 1 areenergized, to channel the outputs of multipliers 85 and 86 along paths90 and 91 to summing junction output points 73a and 74a of themultipliers 73 and 74 respectively. For this purpose the scalar inputsto multipliers 73 and 74 would be R =+X and the scalar input tomultiplier 85 and 86 would be R =+Y The output X would be represented atoutput 79a of amplifier 79 and the output +Y would be represented atoutput 80a of amplifier 80.

The resolver enables the above described modes to be extended to includecontinuous resolution, termed rate mode. For this purpose means may beprovided in combination with the FIG. 1 network to supply an integratedversion of an input dfi/dt to the 0 paths 18 and 22 to the sine andcosine generators. Such means may typically include an integrator 100having its output connected in series with the paths 18 and 22, theintegrator also having inputs at 101 and 102 for positive and negativeversions of d0/dt. Such means may also include apparatus to vary theapplication of at least one of the inputs 101 and 102 to the integratorat times when 0 pasess through the +11 and n' limits, the range betweensuch limits for example describing one complete rotation of a rotatingbody. Such apparatus typically includes an operational amplifier 103,and a switch DA-l, indicated at 104 to switch d0/dt to the input side ofthat amplifier.

Basically, the operation of the resolver in rate mode causes thegenerater sines and cosines to continue through as many 360 degreecycles (as for example of body rotation) as desired. The timing diagramin FIG. 3 shows the DA-l switch turned on when inputs oft-180 degrees,or :1r are reached. Solid line 40 indicative of 6 input shows a sharpchange in voltage direction is required at -7r (100 volts) and +-n-(+100 volts). In FIG. 1, the switched amplifier 103 is connected to thegain of 2 at input 101 of the integrator 100. When 0 arrives as +100volts (+1r) switches DA2 and DA4 will be turned off, and DA1 and DA3will be turned on. Broken line bead 260 indicates optional connection ofthe integrator output to the 6 input point 50.

As +180 degrees is passed by 0, the sine output from generator 10 goesnegative. The -S6 (or sin 0) value connected to the input of thecomparator 105 in FIG. 2 with the S and S ouputs then goes negative.Term S, which is true when S0 is positive, goes false; term S then goetrue. True A, S, and S (cosine going negative) makes DA1 true (theswitching pulse being obtained at 108 in FIG. 2) and the output ofswitched amplifier 103 is applied to the integrator 100. A, S, K, and Sare variously applied via gates 111 and 112, and S is applied via gates110 and 110a. Thet integrator output is now decreasing and will continueuntil an output of 100 volts is reached, at which time DA1 will turn oifand remain off until +100 volts, (or 360 degrees from where is wasturned off), is reached.

The block 106 marked l-shot on the block diagram of FIG. 2 is a variabletime delay device such as a multivibrator used to inhibit DA1 fromswitching. Inputs to the l-shot are +9, 0 and the DA1 or D A 1 termsfrom the DA1 switching flip-flop 107. The output is normally for example-6 volts. The delay flop is triggered at 109 upon a change of state ofswitch DA1, at which time the output goes to 0 volts. Duration of thezero volt output pulse, applied via gates and 110a, is determined by therate of change of 0. If 0 is changing slowly, the duration of the pulseis long; if the 0 changes fast, the pulse is terminated sooner. Thepurpose of the variable pulse length is to inhibit triggering of theflip-flop 107 by noise spikes of the comparator (105) as the sine wavecrosses through zero. The circuit basically generates a voltageproportional to the absolute value of the input angle, and then usesthis voltage to reset the one shot multivibrator. The higher thevoltage, the faster the reset.

The resolver also enables conversion from rectangular to polarcoordinates to yield outputs defined by the following equations:

For this purpose, relays K-l, K-2, K-3 and K4 are energized, the effectaf energizing relays K-l, K-2 and K-3 having been previously discussed.Energization of K4 disconnects the 0 input, connects the output at 79(of multiplier 73) to the 0 input via path 120, disconnects the usualinput of comparator 61 and connects that input with R input, anddisconnects the usual input of comparator 57 and connects that inputwith the R input. In this mode, the R input is X and R input is Y OutputR according to Equation 3 is taken at terminal 80, and output 0according to Equation 4 is taken at terminal 79.

FIG. 4 illustrates a sinusoidal fixed diode function generator of thetype that may be used in the sine and cosine function generators 10 and11. The 0 to +90 degree section 129 of the generator includes breakpointdiodes 130, voltage divider 131, breakpoints 133 in the divider,resistance segments 132, summing junction 134, and operational amplifier135, all connected as shown. The 0 to -90 degree section 129a of thedivider has a corresponding voltage divider and breakpoint diodes, asshown. Input is applied at point 20, and output is taken at 136. FIG. 5illustrates how the lines between breakpoints approximate a portion ofthe sine curve. The generator operates by changing slope gains atpredetermined breakpoints, slope changes being accomplished by theseries resistance slope divider placed in the feedback impedance of theDC operational amplifier 135, as seen in FIG. 4. FIG. 5 shows positiveoutput only, for simplicity. The diodes are chosen to conduct atpredetermined voltages in accordance with the slope changes of theselected sine curve. Operational amplifier 135 is part of the amplifier53 of FIG. 1, or of the amplifier 54 in FIG. 1.

The mode patching portion of FIG. 2 shows the points 1R, 2R, ROT and INVsubject to selective grounding in order to selectively energize therelays K-l K-4 in proper combination for selection of the various modesof operation described above.

I claim:

1. In a resolver, sine and cosine generators with summing paths forfixed amplitude input signals associated with a preselected radian rangefrom +1r to 1r, and for an input signal 6 variable within limitsassociated with the boundaries of said range, switch means connected inseries with certain of said paths to control signal application to thegenerators via said paths, and control logic means to operate saidswitches in response to change of 0 between said limits andcharacterized in that the generators will generate sine and cosineversions of 9, said 0 input paths being directly connected with saidgenerators.

2. In a resolver,

(A) a sine generator and summing paths for sine generator input signalsrepresenting:

(a) an input angle 0 variable between limits delineating an associated211- radian range (c) 1r radians, and (d) --1r radians;

(B) a cosine generator and summing paths for cosine generator inputsignals representing:

(e) (f) -20, and (g) -1r/2 radians;

(C) switch means connected in series with certain of said pathsassociated with the-26, 1r and-1r signals to control application of thesignals -20, 1r, and Tr to the generators via said paths, and

(D) control logic means to operate said switches in response to changesin values of the signal 0 between said limits characterized that thegenerators will generate sine and cosine versions of 0.

3. The resolver of claim 2 in which said control logic includescomparator means to eiiect switch operation controlling application of20, 12' and 1r signals to the sine generator via said paths in responseto a polarity change of the cos 0 output of the cosine generator.

4. The resolver of claim 2 in which said control logic includes means toeffect switch operation controlling application of 29 signal to thecosine generator in response to a polarity change of 0.

5. The resolver of claim 2 in which said control logic includes means toeffect switch operation controlling application of r and 29 signals tothe sine generator in response to passage of 0 through a valuecorresponding to 1r/2 radians.

6. The resolver of claim 2 in which said summing path for 26 signalincludes an inverter.

7. The resolver of claim 2 including network means connected with thesine generator to provide +sin 0 and sin 0 outputs.

8. The resolver of claim 2 including network means connected with thecosine generator to provide +cos 6 and cos 9 outputs.

9. The resolver of claim 2 including multiplier means having inputs andoutputs, certain of said inputs electrically connected to the outputsides of the generators, and paths connected to supply scalar input toother inputs of said multiplier means whereby the multiplier means areoperable to produce at their outputs products of said generator outputsand scalar input.

10. The resolver of claim 9 in which said multiplier means includeprimary multipliers to receive R scalar input and to produce as outputsthe values -R sin 0 and R cos 0, and including means to produce said Rscalar input.

11. The resolver of claim 10 in which said multiplier means includesecondary multipliers connected to receive R scalar inputs and toproduce as outputs the values R cos 6 and R sin 6, and including meansto produce said R scalar input.

12. The resolver of claim 9 in which said multiplier means includeprimary multipliers to receive X scalar input and secondary multipliersto receive Y scalar input, the multiplier outputs being interconnectedto yield output values Y cos 6 X sin 0 and X cos 6+Y sin 0, andincluding means to produce said X and Y scalar input.

13. The resolver of claim 2 including means to supply an input dH/dt,and including means to supply an integrated version of said input 410/dz to said 9 paths to the generators.

14. The resolver of claim 13 in which said last named means includes anintegrator having its output connected in series circuit with the 0paths, the integrator having inputs for positive and negative versionsof dH/dt, and apparatus to very the application of at least one of saidintegrator inputs at times when 6 passas through said limits.

15. The resolver of claim 14 in which said apparatus includes anamplifier connected in series with the integrator at the input sidethereof to receive dO/a't and to produce an output 2d0/dt, and a switchto switch said amplifier output into and out of connection with theintegrator input.

16. The resolver of claim 2 including primary and secondary multipliersconnected to receive input via the generators, paths connected to supplyscalar inputs X and Y to the multiplier, and a feedback path connectedbetween the output of at least one multiplier and the 6 input path,whereby R and 0 outputs are obtainable from certain multipliers, definedapproximately as:

and

17. In a resolver, sine and cosine generators with summing paths forfixed amplitude input signals associated with a preselected radian rangefrom +11 to 'n', and for an input signal 9 variable within limitsassociated with the boundaries of said range, switch means connected inseries with certain of said paths to control signal application to thegenerators via said paths, control logic means to operate said switchesin response to change of 0 between said limits and characterized in thatthe generators will generate sine and cosine versions of 0, a path tosupply an input tie/dz, and means to supply an integrated version ofsaid input dB/dt to 0 input paths to the generators.

18. The resolver of claim 1 including multiplier means having inputs andoutputs, certain of said inputs electrically connected to the outputsides of the generators, and paths connected to supply scalar input toother inputs of said multiplier means whereby the multiplier means areoperable to produce, at their outputs, products of said generatorsoutputs and scalar input.

References Cited UNITED STATES PATENTS 2,697,201 12/1954 Harder 2351972,769,137 10/1956 Creuser. 2,879,002 3/1956 Longerich 235186 2,927,7343/1960 Vance 235-l89 3,044,705 7/1962 Willhite 235-197 3,185,827 5/1965Herndon 235-497 MALCOLM A. MORRISON, Primary Examiner R. W. WEIG,Assistant Examiner US. Cl. X.R.

